AI Infra Interviews logo
Where values live · free reference

Registers

Registers hold values used by an individual GPU thread, such as loop indices, addresses and partial sums. They are backed by a finite register file on the SM.

Thread registers

How it works

The compiler chooses which values remain in registers and for how long. Registers avoid ordinary memory loads for those values, but keeping more values live can reduce the number of resident blocks. Spills use the thread-local address space and can introduce memory traffic.

Work through an example

Unrolling a loop may expose independent arithmetic while keeping more partial sums alive. Measure the resulting instruction schedule, occupancy and spill traffic together.

Where the term can mislead

PTX virtual-register declarations do not directly give the final physical register count. Inspect the compiled kernel’s resource report.

Connect the idea

Take it into practice

Continue with the existing concept, apply it to an interview problem, or follow a course lesson. Access requirements are shown before you open a page.

New to GPUs? Start with the free execution-model concept.

Sources and scope

Examples here are teaching calculations, not measured GPU performance. Consult the linked documentation for the exact device, instruction and tool version. Source review: 25 October 2026.

  1. NVIDIA PTX ISA: instruction semantics and target requirements ↗
  2. NVIDIA CUDA C++ Best Practices Guide ↗