Memory coalescing
Memory coalescing combines the byte addresses requested by active lanes of a warp instruction into the memory sectors needed to serve them.
How it works
On the modern NVIDIA 32-byte sector model, contiguous aligned four-byte accesses by 32 lanes touch four sectors. Larger strides or a shifted starting address can increase that count. Cache reuse and downstream transactions are separate questions.
Work through an example
For 32 FP32 loads, stride one uses four aligned sectors; stride two uses eight; stride 32 uses 32. The useful payload stays 128 bytes, while requested sector bytes become 128, 256 and 1,024.
Same 128 bytes. Different memory requests.
One warp has 32 active lanes. Each lane loads one four-byte value. The number in each cell is its requested 32-byte sector.
Predict it: does shifting contiguous loads by one word matter?
Yes. Aligned contiguous loads span four sectors; shifting the start by one word spans five. The useful payload remains 128 bytes, while requested sector bytes rise from 128 to 160.
Where the term can mislead
Sector count is not a direct measurement of HBM traffic or runtime. Reuse, cache policy and instruction scheduling affect those outcomes.
Connect the idea
Take it into practice
Continue with the existing concept, apply it to an interview problem, or follow a course lesson. Access requirements are shown before you open a page.
New to GPUs? Start with the free execution-model concept.
Sources and scope
Examples here are teaching calculations, not measured GPU performance. Consult the linked documentation for the exact device, instruction and tool version. Source review: 25 October 2026.