Load/store unit
A load/store unit handles memory instructions issued by GPU threads, connecting register operands with the relevant memory path.
How it works
The addresses used by active lanes determine how a warp instruction is broken into memory requests. Caches may satisfy those requests before they reach device DRAM. Instruction issue, address processing and downstream bandwidth are distinct limits.
Work through an example
If a kernel issues many tiny scattered loads, the load/store path can be busy while DRAM bandwidth remains modest. Check sectors per request and dependency stalls before blaming the advertised HBM rate.
Where the term can mislead
A high-level memory-throughput percentage can summarize a busy subunit. It is not necessarily the percentage of DRAM bandwidth consumed.
Connect the idea
Take it into practice
Continue with the existing concept, apply it to an interview problem, or follow a course lesson. Access requirements are shown before you open a page.
New to GPUs? Start with the free execution-model concept.
Sources and scope
Examples here are teaching calculations, not measured GPU performance. Consult the linked documentation for the exact device, instruction and tool version. Source review: 25 October 2026.