Core

Memory Coalescing

Coalescing combines a warp’s nearby memory accesses into fewer transactions. Inspect addresses across lanes to understand how much data each access actually fetches.

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RELATED CONCEPTS

GPU Memory Hierarchy CUDA Programming Model Shared Memory and Bank Conflicts Profiling with Nsight Memory-Bound vs Compute-Bound Kernels Parsing Kernel Traces and Logs

LESSONS THAT TEACH THIS

Kernels and the MachineCoalescing is the whole of memory performance, stated once15 min→Kernels and the MachineCapstone: take a slow kernel to the roof and write the analysis300 min→Kernels and the MachineMap coordinates before moving bytes18 min→

PRACTICE THIS IN REAL QUESTIONS

CUDA, Triton & Kernel EngineeringGiven the addresses each thread in a warp touched, classify the access pattern: coalesced, strided or random. Write the classifier.→CUDA, Triton & Kernel EngineeringWhat is memory coalescing, why does a strided access pattern hurt, and how do you see it in a profiler?→CUDA, Triton & Kernel EngineeringTranspose a large matrix at close to copy bandwidth. Why is the naive version slow, and what does each fix buy?→CUDA, Triton & Kernel EngineeringA CUDA upgrade improves warm runs but slows the first request. Would you ship it?→CUDA, Triton & Kernel EngineeringA GEMM launches 96 tiles into 80 execution slots. Should you split K?→CUDA, Triton & Kernel EngineeringAn AI-generated kernel passes random tests and claims a 3x speedup. What would you verify?→