Core

Memory Coalescing

A warp's 32 threads issue one memory request together, and the hardware serves it in 32-byte sectors. Coalescing is arranging addresses so those sectors are full of bytes the warp will use. It decides whether a bandwidth-bound kernel moves at the HBM rate or at an eighth of it, and it is the pattern NVIDIA's trace-classification interview question tests.

a free account unlocks the core curriculum tier · no card

RELATED CONCEPTS

GPU Memory Hierarchy CUDA Programming Model Shared Memory and Bank Conflicts Profiling with Nsight Memory-Bound vs Compute-Bound Kernels Parsing Kernel Traces and Logs

PRACTICE THIS IN REAL QUESTIONS

CUDA, Triton & Kernel EngineeringGiven the addresses each thread in a warp touched, classify the access pattern: coalesced, strided or random. Write the classifier.→CUDA, Triton & Kernel EngineeringWhat is memory coalescing, why does a strided access pattern hurt, and how do you see it in a profiler?→CUDA, Triton & Kernel EngineeringTranspose a large matrix at close to copy bandwidth. Why is the naive version slow, and what does each fix buy?→CUDA, Triton & Kernel EngineeringWhen do you write a kernel in Triton, and when do you have to drop down to CUDA?→GPU & Accelerator ArchitectureA kernel runs at 25% occupancy. Is that a problem? Walk me through what occupancy buys and when you would leave it low on purpose.→GPU & Accelerator ArchitectureWalk me through the CUDA execution model: what are grids, blocks and warps, and what does the hardware actually schedule?→