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Transpose a large matrix at close to copy bandwidth. Why is the naive version slow, and what does each fix buy?

Trace how a shared-memory tile turns coalesced input rows into coalesced output rows. Then separate global sector footprints, shared-bank conflicts and measured bandwidth, including the cost of handling edge tiles.

Updated Oct 2026 · Learn how AI infrastructure works through explanations, worked examples and diagrams, then practise applying it to interview questions.

Trace how a shared-memory tile turns coalesced input rows into coalesced output rows. Then separate global sector footprints, shared-bank conflicts and measured bandwidth, including the cost of handling edge tiles.

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Work through the numbers

Change the assumptions in a free calculator, then explain what the result establishes and what still needs measurement.

The concepts behind this question

Use these concept explanations to review the ideas behind this question.

Advanced
⚡ Kernels & Compilers🔒 Premium
Shared Memory and Bank ConflictsShared memory lets threads in a block exchange and reuse data. Bank conflicts occur when an access needs multiple distinct words from the same bank.
Foundational
🧩 GPU & Accelerator Architecture
GPU Memory HierarchyTrace storage scope and data reuse from registers through shared memory, caches and HBM. Worked register and traffic examples explain why a source-level load is not automatically an HBM transfer.
Core
⚡ Kernels & CompilersSign in
Memory CoalescingCoalescing combines a warp’s nearby memory accesses into fewer transactions. Inspect addresses across lanes to understand how much data each access actually fetches.
Advanced
⚡ Kernels & Compilers🔒 Premium
Tiled Matrix MultiplicationTiled matrix multiplication reuses input values across many output calculations. Shared-memory and register tiles reduce repeated data movement while consuming limited on-chip resources.
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FEDITOR'S NOTE

Explain how ownership changes between load and store, derive the 32-to-33-word bank mapping, and use copy bandwidth as a measured reference rather than a universal timing guarantee.

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