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NVIDIA CUDA, Triton & Kernel Engineering interview questions

Practise cuda, triton & kernel engineering for NVIDIA AI Infrastructure Engineer roles. Coalescing, shared memory and bank conflicts, occupancy, fusion, tiled GEMM, FlashAttention internals, Triton, CUTLASS, Nsight profiling and torch.compile: the live-coding and take-home round at NVIDIA, Fireworks, Together and the labs' performance teams. Questions tagged to NVIDIA appear first, followed by additional practice from our CUDA, Triton & Kernel Engineering track. Company tags indicate preparation relevance, not confirmed interview appearances. Confirm the current interview format with your recruiter.

PREPARATION CONTEXT · Explain GPU memory access and synchronization with a correct worked kernel. Sources and confidence in the NVIDIA guide →

CUDA, Triton & Kernel Engineering questions tagged to NVIDIA

17 questions · 7 unlocked for you

Additional CUDA, Triton & Kernel Engineering practice

These questions cover the same topic and are not tagged to NVIDIA. Use them to practise applying the ideas in a different situation.

6 questions · 3 unlocked for you

Concepts for CUDA, Triton & Kernel Engineering preparation

These concept explanations cover the ideas used in the questions. Check each card for its access level.

Foundational
CUDA Programming ModelCUDA programs launch GPU kernels from host code. Thread indexing, memory access and stream ordering determine whether the result is correct.
Core
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Memory CoalescingCoalescing combines a warp’s nearby memory accesses into fewer transactions. Inspect addresses across lanes to understand how much data each access actually fetches.
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Shared Memory and Bank ConflictsShared memory lets threads in a block exchange and reuse data. Bank conflicts occur when an access needs multiple distinct words from the same bank.
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Occupancy and Register PressureOccupancy measures how many warps are resident relative to an SM’s limit. Registers, shared memory and launch shape constrain it, but higher occupancy is not always faster.
Foundational
Kernel FusionKernel fusion combines operations so intermediate results can stay on-chip. It can reduce memory traffic and launch overhead, but may increase resource pressure.
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Tiled Matrix MultiplicationTiled matrix multiplication reuses input values across many output calculations. Shared-memory and register tiles reduce repeated data movement while consuming limited on-chip resources.
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FlashAttention InternalsFlashAttention computes exact attention in tiles without storing the full score or probability matrix in device memory. Follow the running softmax state, understand why inputs can still be reread, and distinguish the mechanisms introduced in the first three papers.
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CUTLASS and Tensor Core KernelsCUTLASS provides components for building GPU matrix kernels. It is useful when the required precision, batching or fused operations need more control than a library call offers.
NVIDIA CUDA, TRITON & KERNEL ENGINEERING FAQ

This collection includes practice questions such as "Write a CUDA vector add and explain the launch: grid math, the bounds check, and why the copies dominate.", "What is memory coalescing, why does a strided access pattern hurt, and how do you see it in a profiler?", "Given the addresses each thread in a warp touched, classify the access pattern: coalesced, strided or random. Write the classifier.". Company tags describe relevance to preparation; they do not confirm that NVIDIA asked these questions. Check each question for answer access.

Other topics for NVIDIA preparation

Explore the other topics mapped to NVIDIA in our preparation guide.

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