AMD AI Infrastructure Engineer interview questions

Separate storage scope from physical backing, then follow a warp through adjacent and strided loads. Count useful bytes and requested sectors before inferring HBM traffic or speed.

Derive HBM bandwidth from interface width and pin rate, then connect it to a model that actually fits. Separate raw interface capacity from measured decode time.

See how 192 GB changes replica shape, calculate KV headroom with exact units, and compare feasible deployments at equal quality and latency.

HIP can translate many CUDA interfaces, but it cannot validate the assumptions inside a kernel. Check thread-group widths, masks, shared state and numerical behavior before tuning the MI300X implementation.

Validate the exact model, accelerator generation and serving features. Separate packed storage from kernel execution, derive the real memory fallback, and compare qualified throughput and total migration cost.

Explain packet spraying through a small path-collision model, then separate transport features from measured performance and a supported fabric purchase.

Trace a grid into blocks and warps, then distinguish resident work from ready work. Derive an occupancy limit without treating it as a speed target.

Follow the running maximum and weighted sum across attention tiles, with executable arithmetic and an honest memory-traffic comparison.

Count two matrix shapes to derive the H100 ridge, throughput ceilings and time floors. Compare an illustrative measurement with its bound before deciding what to optimize.

Derive resident-block limits and distinguish resident warps from ready work before trading registers for more occupancy.

Derive the weight-only shortcut, then add KV traffic and feasible eight-GPU placement. A worked latency floor shows why batch size alone cannot establish the decode bottleneck.

Choose between supported InfiniBand and RoCE designs using workload tests, congestion behavior and a complete cost model.

Normalize link directions, count collective bytes, and see why a gradient reduction can outlast its real overlap window.

Trace stable row normalization, handle independent strides and fully masked inputs, then separate fusion traffic from measured speed.

Separate quota, borrowing, reclaim latency and fairness, with a demand-conserving example of when pooling improves utilization.

Compare useful parallel work, data movement and reuse. A synthetic CPU/GPU crossover shows why a faster kernel can still lose the end-to-end request.

Follow a four-GPU request from advertised capacity to concrete devices, and see why free GPUs across nodes cannot satisfy one pod.

DRA gives the scheduler device claims and attributes to work with. Compare that with extended-resource counts, then check the deployed driver and controller support before promising sharing, partitioning or gang placement.

Map a non-divisible array onto blocks, guard the final 189 threads, and separate kernel traffic from host transfers without inventing measured timings.

Follow operand tiles into a matrix-multiply-accumulate instruction. Explain why odd dimensions and low tensor activity do not prove a fallback.

Follow intermediate tensors through separate and fused stages, calculate the traffic and whole-block bounds, and check spills and numerical behavior.

Compare the mechanisms in FlashAttention versions 1, 2 and 3: IO savings, work partitioning, asynchronous dependencies and FP8 accuracy.