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Port a hand-written CUDA kernel to MI300X. What translates mechanically, and what silently computes the wrong answer?

HIP can translate many CUDA interfaces, but it cannot validate the assumptions inside a kernel. Check thread-group widths, masks, shared state and numerical behavior before tuning the MI300X implementation.

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HIP can translate many CUDA interfaces, but it cannot validate the assumptions inside a kernel. Check thread-group widths, masks, shared state and numerical behavior before tuning the MI300X implementation.

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Work through the numbers

Change the assumptions in a free calculator, then explain what the result establishes and what still needs measurement.

The concepts behind this question

Use these concept explanations to review the ideas behind this question.

Advanced
🧩 GPU & Accelerator Architecture🔒 Premium
AMD Instinct and ROCmAMD Instinct GPUs offer substantial memory capacity and bandwidth. Workload performance also depends on ROCm, the model implementation and the kernels available for the chosen device.
Foundational
⚡ Kernels & Compilers
CUDA Programming ModelCUDA programs launch GPU kernels from host code. Thread indexing, memory access and stream ordering determine whether the result is correct.
Core
⚡ Kernels & CompilersSign in
Memory CoalescingCoalescing combines a warp’s nearby memory accesses into fewer transactions. Inspect addresses across lanes to understand how much data each access actually fetches.
Advanced
⚡ Kernels & Compilers🔒 Premium
Shared Memory and Bank ConflictsShared memory lets threads in a block exchange and reuse data. Bank conflicts occur when an access needs multiple distinct words from the same bank.
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FEDITOR'S NOTE

Explain which assumptions affect correctness and which affect performance. Distinguish a hardware wavefront from a deliberate logical subgroup, then validate the port before changing tiles or pipelines.

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