192 GB of HBM on an AMD CDNA 3 accelerator. The memory is useful only after the model’s kernels and serving engine work on the ROCm target.
Memory per accelerator
192 GB
HBM3
Memory bandwidth
5.3 TB/s
Published peak, not measured application throughput
Remember this
The checked GLM-5.3-Flash vLLM ROCm image is gated to gfx950; the recipe says MI300X/MI325X support is pending. These cards can fit many models, but that does not prove this particular recipe works.
When this is a sensible choice
Start here if…
Use MI300X for a supported ROCm deployment where 192 GB reduces the number of memory shards. A nominal 70B BF16 weight payload leaves about 52 GB before runtime and state, much more than on H200.
Choose another configuration if…
Do not assume a CUDA-only fused kernel has an equivalent ROCm implementation. Validate attention, experts, collectives and any speculative-decoding path before treating a memory calculation as a deployment.
Specifications with their boundaries attached
Architecture
CDNA 3
Memory
192 GB HBM3
Memory bandwidth
5.3 TB/s per accelerator
Peak compute
1,307.4 TFLOPS BF16; 2,614.9 FP8, dense
Scale-up interconnect
Infinity Fabric; ROCm table lists 896 GB/s ring aggregate
Host attachment
PCIe 5.0 x16; OAM server module
Power
750 W
Partitioning
ROCm compute/memory partition modes; not NVIDIA MIG
Catalogue status
Documented product
Compute figures are theoretical peaks at the stated precision. Dense and structured-sparse rates must not be mixed. Bandwidth labelled bidirectional combines both directions. See the source documents.
Follow the bytes · conceptual topology
Three bandwidths, three different jobs
Local memory192 GB HBM3
↔
Compute enginesExecute kernels on these bytes
① Memory bandwidth: 5.3 TB/s
Accelerator AOwn local memory
↔
Accelerator BOwn local memory
② Scale-up: NVLink, Infinity Fabric or PCIe Infinity Fabric; ROCm table lists 896 GB/s ring aggregate
Server AAccelerators + host
↔
Server BAnother fabric domain
③ Scale-out: NICs + switches + placement InfiniBand, RoCE, EFA or provider-specific transport
A 400 Gb/s NIC has a 50 GB/s raw line-rate equivalent before overhead. A 900 GB/s bidirectional NVLink figure counts traffic in both directions. Neither is the bandwidth at which a GPU reads its own HBM. This diagram explains the boundaries; it is not a wiring diagram for a particular cloud machine.
Where it appears in provider documentation
No provider configuration has been verified for this exact variant in this reference. Consult the linked manufacturer documentation; catalogue absence here is not evidence that the hardware is unavailable.
Model fit and software support
These publisher or serving-engine documents mention this hardware family. They have not been reproduced on our machines.
753B · total parameter proxy · active count not used for sizing
753B is the Hub’s rounded tensor count, not a claim that every tensor uses FP8. The 753 GB raw 8-bit estimate excludes scales, caches and workspace. Do not reuse Flash’s architecture or serving flags for this model. The vLLM recipe describes eight H200s for FP8 and eight B200s for full context. Its 0.29.0+ header conflicts with the 0.28.0 installation; pin a working build. A 32-sequence scheduling cap does not prove 32 concurrent million-token requests. The mixed NVFP4 variant is reported at about 465 GB, larger than an all-four-bit estimate.
Official repository initial upload is labelled 0828. Date evidence ↗
What is the memory floor?
Start with total parameters, then add the memory the workload needs. This arithmetic does not certify a serving configuration. All output sizes below are decimal GB.
Override device capacity with the memory exposed by your allocation, particularly for cloud B300 and partitioned devices. The starting 32 GB budget and 15% reserve are editable teaching assumptions. They are not measurements for the selected model. Mixed-precision tensors, quantization scales, vision encoders and draft models can increase the weight payload.
320 GB
Raw weights only 320B × 8 bits ÷ 8
163.2 GB
Budget per device 192 GB × (1 − 15%)
3 devices
Arithmetic lower bound round up ((weights + 32) ÷ budget)
WeightsCache + runtimeRemaining budget
This assumes perfectly balanced sharding. A result of three does not prove that a three-device parallel layout is supported. Check layer/expert divisibility, actual allocatable memory, precision kernels and the fabric before renting.
320B is the model card’s total; 18B active is not its storage size. The vLLM recipe reports about 306 GiB for the native FP8 checkpoint. Hopper requires BF16 KV for this model; the documented ROCm path targets gfx950, not every Instinct GPU. Read the model source ↗
For full training, also budget gradients, optimizer states, activations and communication buffers. The inference weight estimate above is insufficient.
Tokens per second, TTFT and TPOT are not certified for this hardware in our reference. Use the benchmark checklist to compare an exact model, software revision and workload.
Nearby memory capacities, different tradeoffs
These are comparison candidates selected by memory capacity, not performance rankings or drop-in replacements.
A rack-scale system, not a single PCIe card. This comparison uses 186 GB per GPU from GCP’s four-GPU VM configuration; the full rack includes 72 GPUs and 36 Grace CPUs.
Hopper with a larger, faster memory system: 141 GB at 4.8 TB/s. Its value over H100 is easiest to see in memory capacity and memory traffic.
Sources and review scope
Manufacturer and cloud documentation checked 2026-09-12. We reviewed specifications and the stated product boundaries; we did not run training or serving benchmarks on this device. Cloud memory and availability can differ by configuration.
Include your access date when citing a changing specification. Link to the specification section for hardware figures or the explanation for a sizing or workload decision.
Research method and limits
We compile manufacturer specifications, cloud documentation, model cards and serving recipes. The reference preserves source units and distinguishes individual devices from nodes and racks. Conflicting figures and unknown fields remain labelled.
Our contribution is the comparison, unit reconciliation, worked arithmetic and workload explanation. Published peaks are vendor specifications. Calculator results are estimates under the displayed assumptions. Neither is a measurement from our own accelerator lab.
For a manufacturer’s specification, consult the original source documents. Cite our page when using its analysis, and retain primary-source attribution for underlying figures. This curated reference does not establish market share, live availability or a universal performance ranking.
Found a discrepancy? Send a correction with the page URL, exact variant, disputed figure and supporting primary document.
