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Oracle Cloud Infrastructure AI Infrastructure Engineer interview questions

Oracle Cloud Infrastructure sells some of the largest GPU superclusters available for rent and hires the engineers who build and operate them: bare-metal GPU fleets, RDMA cluster networking, storage for training, and the Kubernetes and orchestration layers customers use to run training and inference at scale. The work is hyperscale fleet engineering with a customer in front of it, closer to a GPU cloud than to a lab. We have not found a reliable public breakdown of OCI's AI infrastructure loop and do not list unconfirmed rounds; prepare fleet operations, RDMA fabrics and scheduling, and confirm the format with the recruiter.

HYPERSCALERS AND GPU CLOUDS

They rent capacity to everyone else, so the interview is about fleets, tenants and the physical plant rather than any single model.

Loop leans on: Fleet scale, schedulers, networking, capacity, reliability. Compare the other hyperscalers and gpu clouds

The Oracle Cloud Infrastructure AI Infrastructure Engineer interview process

Limited public data
RoleOCI GPU infrastructure engineer
No reliable public breakdown of the loop; requirements inferred from OCI's GPU supercluster offering. Rounds unconfirmed.
WHAT THEY'RE EVALUATING
  • Bare-metal GPU fleets and RDMA cluster networking
  • Kubernetes and orchestration for customer training and inference

Compiled from our research and publicly available information (candidate reports and company interview guides). Interview loops change and are continuously iterated, and they vary by team, level, and region. Treat this as directional preparation, not an official spec, and confirm the exact rounds with your recruiter or hiring point of contact.

Oracle Cloud Infrastructure AI Infrastructure Engineer salary

What we can trace, labelled by where it came from. We publish a band only where there is a source behind it, so some of this page is a gap rather than a number.

NO TRACEABLE BAND

We have not found a compensation figure for this role at Oracle Cloud Infrastructure that we can trace to an employer posting or a public aggregator. Rather than publish an estimate, we are naming the gap. Their careers page is the authority, and postings in some jurisdictions are required to state a range.

HIRING FROM INDIA
Multinational with an India engineering centre

An established India presence, usually Bengaluru, Hyderabad or Pune, hiring on a local band with the parent company's level structure. Far more attainable than the global-remote route, with listed-company equity and the usual multinational benefits.

LEVELREPORTED FOR THIS EMPLOYER TYPE
Early career (IC1-IC2 equivalent)₹26 LPA - ₹45 LPA
Senior (IC3 equivalent)₹37 LPA - ₹85 LPA
Staff and above (IC4+ equivalent)₹69 LPA - ₹1.4 Cr

Reported total compensation for NVIDIA software engineers in India by level, per levels.fyi self-reports (accessed September 2026; IC3 median about ₹62 LPA, IC4 median about ₹94 LPA), used as the reference for this employer type. Not a figure reported for this company or for this exact title; bands vary by internal level and by company.

Full method, US bands by level, and the three India tiers side by side are in the AI infra salary guide, including what actually moves your number between these tiers.

Questions modeled on Oracle Cloud Infrastructure loops

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Go deeper on the topics Oracle Cloud Infrastructure's loop tests

The tracks that map to a Oracle Cloud Infrastructure AI Infrastructure Engineer loop, ordered easy to hard.

The concepts Oracle Cloud Infrastructure's AI Infrastructure Engineer loop assumes you know

The vocabulary and mental models behind Oracle Cloud Infrastructure's questions, from our curriculum. Start with the foundations free; the deeper, interview-defining ideas are part of premium.

SCHEDULING & ORCHESTRATION

Foundational
Kubernetes GPU SchedulingKubernetes knows nothing about GPUs until something tells it. The NVIDIA device plugin advertises each node's GPUs as a countable resource, the scheduler matches a pod's request to a node with enough of them, and the container runtime wires the device in. That model is enough for one job per GPU and breaks the moment you need sharing, topology or multi-node placement, which is where Dynamic Resource Allocation, the GPU Operator and the batch schedulers come in. Knowing which layer does what is the platform interview's opening question.
CoreSign in
MIG, MPS and Time-SlicingA whole H100 is far more than a notebook, a small inference service or a CI job needs, and giving each of them a card leaves most of the fleet idle. Three mechanisms share a GPU, and they differ in what they isolate: MIG partitions the hardware into up to seven slices with their own memory and compute, MPS lets several processes share one GPU's SMs concurrently with no memory isolation, and time-slicing context-switches between processes with no isolation at all. The choice is the isolation the workload needs against the utilization the platform wants.
Advanced🔒 Premium
Gang Scheduling with Kueue and VolcanoA distributed training job is 64 pods that start together or not at all: if 40 are running and 24 are Pending, the 40 hold their GPUs idle at a collective barrier waiting for ranks that may never come, and two such jobs can deadlock a whole cluster. Gang scheduling makes the job the unit of admission. Kueue and Volcano add queues, quotas, priorities and preemption on top, which is what turns a pile of GPUs into a platform several teams can share without starving each other.
Advanced🔒 Premium
Topology-Aware SchedulingTwo placements of the same 64-GPU job can differ by 2x in step time: one keeps every tensor-parallel group on a single NVSwitch node and every data-parallel ring on a single rail, the other scatters ranks across racks and pushes per-layer traffic through the spine. The scheduler is the only thing that can prevent the second placement, because the framework maps ranks to whatever GPUs it is handed. Topology-aware scheduling means the scheduler knows the hierarchy (NVLink domain, rail, rack, spine block) and places gangs to keep traffic low in it.

NETWORKING & STORAGE

Foundational
NCCL and Collective AlgorithmsNCCL is the library every PyTorch collective lands in, and its choice of ring or tree, channel count and protocol decides whether an all-reduce runs at fabric speed or at a third of it. Knowing what NCCL_DEBUG=INFO prints, and which environment variable changes which decision, is the difference between tuning a cluster and guessing at it.
CoreSign in
RDMA, InfiniBand and RoCEv2Training across nodes moves hundreds of gigabytes per step, and a CPU-driven TCP stack cannot feed a 400 Gb/s link. RDMA lets a NIC write straight into a remote GPU's memory with no kernel and no copies, and it runs over two fabrics: InfiniBand, which is lossless by design, and RoCEv2, which is Ethernet made lossless by configuration. The choice is operational as much as technical, and the numbers that decide it are per-GPU bandwidth, the collective's volume, and who will debug a pause storm at 3 a.m.
Advanced🔒 Premium
Rail-Optimized and Fat-Tree FabricsA GPU cluster's network is built from two ideas: a fat tree (Clos) that gives every node a path to every other node with a chosen amount of oversubscription, and rail optimization, which wires GPU i of every node to the same leaf switch so the collectives that dominate training stay one hop away. Sizing one is arithmetic on port counts, and the interview question is usually that arithmetic: how many switches, what oversubscription, and where the NVLink domain ends and the fabric begins.
Advanced🔒 Premium
Congestion Control for AI FabricsCollective traffic is the worst case a network can see: hundreds of senders transmit to the same receiver at the same instant (incast), every flow is large and long-lived, and RDMA cannot tolerate a dropped packet. Congestion control is the set of mechanisms (PFC, ECN with DCQCN, adaptive routing, packet spraying) that keep queues from overflowing without stalling the fabric. On plain Ethernet a busy all-reduce can fall to about 60% of link rate; with a tuned control loop it holds above 90%. Reading the counters that show which one you have is the on-call skill.

FLEET RELIABILITY & OBSERVABILITY

Foundational
GPU Failure Modes and XID ErrorsWhen a GPU misbehaves, the NVIDIA driver writes an XID line to the kernel log, and the number on that line is the first and often the only clue to what happened. Fleet engineers learn a dozen of them the way doctors learn a dozen lab values: 13 and 31 are almost always the application, 48 and 95 are memory that needs a reset, 63 and 64 are the row remapper reporting or failing, 74 is the NVLink fabric, 79 is a GPU that has vanished from the PCIe bus. This page gives the taxonomy, the decision for each (retry, reset, drain, RMA), and the derivation of how often a big fleet should expect each.
CoreSign in
DCGM and GPU TelemetryNVIDIA's Data Center GPU Manager reads a GPU's counters, runs its diagnostics and exports both to the monitoring stack, and nearly every fleet's dashboards and alerts are built on it. The skill is knowing which of its hundreds of fields carry signal: the profiling metrics that say whether the tensor cores are busy (not the utilization number everyone reads first), the error counters that predict a failure, the throttle reasons that explain a slow step, and the diagnostic levels that decide whether a node returns to the pool. This page walks those fields, derives an MFU estimate from them, and gives a fleet's alert thresholds.
Advanced🔒 Premium
ECC, Row Remapping and Memory ErrorsHBM stacks flip bits, and the difference between a fleet that shrugs and one that loses a training step to corruption is error-correcting codes plus the machinery that retires bad memory before it produces a double-bit error. A single-bit error is corrected silently and counted; a double-bit error is detected, kills the process, and on Ampere and later triggers the row remapper to swap the failing row for a spare at the next reset. This page explains the codes, the remapper's states, how to read the counters as a prediction of failure, and the RMA rules a fleet applies.
Advanced🔒 Premium
NVLink and Fabric FaultsThe links between GPUs are the part of a training node with the most connectors, the highest signalling rates and the least forgiveness: one marginal NVLink cable or one NVSwitch port turns an eight-GPU node into a straggler that slows a thousand-GPU job, and the symptom arrives as an NCCL timeout three layers away from the cause. This page covers what the links are, what their error counters mean, how a fault shows up in NCCL and in step time, how to isolate it to a GPU, a cable or a switch, and the arithmetic of why one degraded link is a whole-job problem.

NAPKIN MATH & CAPACITY

Foundational
Model Memory FootprintThe first calculation in almost every AI infra loop: how many bytes does this model occupy, for inference and for training, and does it fit on the card in front of you? Inference is parameters times bytes per parameter (2 in bf16), plus a KV cache that grows with users. Training is 16 bytes per parameter before activations. A 70B model is 141 GB to serve and 1.13 TB to train, and a reader who can produce those two numbers from the parameter count, with the reasoning, has passed the first five minutes of the estimation round.
Foundational
KV Cache SizingThe KV cache is the memory that decides how many users a serving replica can hold and how long their context can be. Its size per token comes from four numbers in the model's config file (layers, KV heads, head dimension, bytes per element) and one formula; multiplied by context and concurrency it is the number every capacity plan is built on. This page derives it, works it for four models including an MLA one, and shows the two places candidates get it wrong by a factor of eight.
Foundational
Training FLOPs: 6NDThe compute needed to train a language model is six floating-point operations per parameter per token: two for the forward pass and four for the backward. Multiply by the parameter count and the token count and you have the whole run's compute, which is the number every fleet-sizing, time-to-train and cost question starts from. This page derives the 6, states the attention correction and when it matters, and shows where the 2N of inference comes from, so the reader can rebuild the formula rather than recall it.
Advanced🔒 Premium
Bandwidth-Bound Decode ThroughputBecause decode reads every weight once per step, its speed is a division: memory bandwidth over bytes per step. That one formula gives single-stream tokens per second for any model on any card, the batch curve that flattens at the ridge point, the effect of quantization, and the point where the KV cache rather than the weights becomes the thing being read. This page derives it, works it for a 70B model on four accelerators, and shows how to read a vendor throughput claim against it.

Where to apply, and official Oracle Cloud Infrastructure resources

Straight from Oracle Cloud Infrastructure: open roles and the company's own hiring guidance. Prep here, then apply there.

External links to Oracle Cloud Infrastructure's own pages. Roles and processes change; always confirm on the official site.

ABOUT THE ROLE
ORACLE CLOUD INFRASTRUCTURE INTERVIEW FAQ
Does Oracle hire AI infrastructure engineers?

Yes, for the GPU superclusters and the networking, storage and orchestration around them. Titles vary; search the Oracle careers site for GPU, HPC, RDMA and OCI AI infrastructure roles.

What does the Oracle AI infrastructure interview test?
What is the Oracle AI infrastructure engineer salary?

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