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TPU Architecture and Systolic Arrays

TPUs use matrix units and compiler-managed execution to run machine-learning workloads. Memory, shapes and inter-chip communication still determine how efficiently a model runs.

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LESSONS THAT TEACH THIS

Kernels and the MachineOn a compiled accelerator, the program is the unit, not the kernel22 min→

PRACTICE THIS IN REAL QUESTIONS

GPU & Accelerator ArchitectureYou have trained on GPUs. What transfers to training on TPUs, and what do you have to relearn?→GPU & Accelerator ArchitectureExplain how a systolic array computes a matrix multiply. Why is it efficient, and why does it want big square tiles?→Distributed Training & ParallelismHow is training on TPUs with JAX different from training on GPUs with PyTorch? What do you stop doing by hand?→Open-Weights Models & Serving EnginesYou serve a model with vLLM on GPUs. What changes when you move the same model to TPUs?→Distributed Training & ParallelismA PyTorch team wants to train on TPUs. Do they rewrite in JAX with MaxText, use PyTorch/XLA, or wait for TorchTPU?→Open-Weights Models & Serving EnginesYou must serve a frontier open-weights model on non-NVIDIA accelerators. Plan it.→